1. Technical Field
The present invention relates to a surface-emitting semiconductor device used as a light source of optical data processing or high-speed optical communication, and a method of manufacturing thereof.
2. Related Art
Recently, in technical fields such as optical communication or optical storage, there has been a growing interest in Vertical-Cavity Surface-Emitting Lasers (hereinafter referred to as VCSELs).
VCSELs have excellent characteristics which edge-emitting semiconductor lasers do not have. For example, VCSELs have a lower threshold current and smaller power consumption. With VCSELs, a round light spot can be easily obtained, and evaluation can be performed while they are on a wafer, and light sources can be arranged in two-dimensional arrays. With these characteristics, demands as light sources especially in the communication field have been expected to be arising.
A structure of a VCSEL chip of a related art is shown in FIGS. 21A and 21B. FIG. 21A is a plan view of a VCSEL chip 1, and FIG. 21B is a cross sectional view of FIG. 21A taken along line A-A. The VCSEL chip 1 includes an n-side electrode 3 on the back surface of, for example, a GaAs substrate 2, and on the front surface of the GaAs substrate 2, multiple semiconductor layers of AlGaAs-type are stacked. By etching the stacked semiconductor layers, a cylindrical post 4 is formed on the substrate. After forming the post 4, an interlayer insulating film 5 is patterned to cover the post 4 and exposed AlGaAs layer close to the post. On the interlayer insulating film 5, an electrode pad 6 and an extraction electrode 7 are formed, and the extraction wiring 7 is electrically coupled to a p-side electrode in the post 4.
Due to hygroscopicity of Al in the AlGaAs layer, the interlayer insulating film 5 may be delaminated from the undercoating, and the post 4 may be released from the substrate 2. Especially when the substrate 2 is diced, stress may be created in an interface between the AlGaAs layer and the interlayer insulating film 5 due to, for example, difference in thermal expansion coefficient. From the interface, moisture may enter and thus delamination of the interlayer insulating film 5 may be enhanced. This may damage the electrode pad 6 and the extraction wiring 7 formed on the interlayer insulating film 5, and may cause failures.
FIG. 22 shows an example in which multiple VCSELs are formed on a wafer W. Each VCSEL is cut out from the wafer along dicing lines L into individual chips. As shown in FIG. 23, the chip has chipping in which its cutting plane 20 becomes jagged. When wet high temperature operating life test is conducted for such a VCSEL chip, at a temperature of 85 degrees Celsius and a humidity of 85%, for example, a crazing or crack 22 may grow from the cracked portion of cutting plane 20 toward incide of the chip. Almost the whole area of the wafer including a post 28 is covered with an interlayer insulating film 24, and on the interlayer insulating film 24, an electrode pad 26 is formed. When the crack 22 grows incide, the interlayer insulating film 24 may be delaminated. This may damage the electrode pad 26 and the extraction wiring. Also, unwanted stress may be applied on the post 28, which may cause device failure.